1. Field of the Invention
The present invention relates to a wafer stage, and to a technique to fix an outer-ring on the wafer stage to improve the thermal conductance between the outer-ring and an electrode arranged in the wafer stage.
2. Description of the Related Art
Plasma assisted wafer processing technique is well-established process in the fabrication of semiconductor devices on Si or other wafers or substrates. Most of the wafer processes are carried out at a controlled temperature because desired chemical and/or physical reactions are occurred only at a specific temperature or a temperature range. The wafer temperature is normally controlled by placing the wafer on a temperature-controlled electrode arranged in a wafer stage while the wafer is pressed to the electrode by mechanical or electrostatic fixing techniques. The wafer stage has a thermal mechanism that gives heat to the electrode. In addition, a high-pressure gas is fed into a very thin gas reservoir made between the wafer and the electrode in order to increase the thermal conductance between them. This technique is generally good enough to maintain the wafer temperature within a desired temperature range.
Some of the wafer processes are very sensitive to wafer temperature as it changes the gas chemistry over the wafer surface. For these processes, not only the wafer temperature is important, but also the temperatures of other surfaces, which lies very close to the wafer, particularly an outer-ring, are also important. If the outer-ring that lies around the wafer is at a different temperature, a different process occurs on the outer-ring surface and generates different gas chemistry on its surface. This adversely affects the chemistry on the wafer surface for the outermost region of the wafer surface specially. These problems are explained in detail by considering a conventional wafer stage used in dielectric etching process. Two different conventional examples are explained as follows.
FIG. 6 shows a conventional wafer stage 100 normally used in dielectric etching as one example. The wafer stage 100 is comprised of an electrode 101, a thin dielectric plate 102 attached to the upper surface of the electrode 101, an outer-ring 103 and dielectric shields 104, 105 and 106. Within the electrode 101, a plurality of canals 107 is made to flow a temperature-controlled liquid in order to control the temperature of the electrode 101. The electrode 101 is connected to a rf power source 109 via a matching circuit 108. A wafer not shown in FIG. 6 is placed on the dielectric plate 102. It is noted that one may supply a DC voltage to the electrode 101 from a DC power source. This is to electrostatically clamp the wafer onto the dielectric plate 102. However, even in the absence of additional DC voltage applied to the electrode 101, wafer may be electrostatically clamped onto the dielectric plate 102 by the self-bias voltage generated on the wafer surface.
During the operation of the wafer stage 100 in the dielectric etching process, the rf power is applied to the electrode 101 in order to generate a self-bias voltage (Vdc) on the wafer surface. The electric field generated due to the self-bias voltage Vdc accelerates ions on to the wafer surface. The bombardment of the ions causes etching of the wafer surface. In the dielectric etching process, there are two different chemistries on the wafer surface; one is ion-assisted etching and the other is neutral radical or molecule-assisted film deposition. For example, with the conventional gases such as C4F8/Ar/O2, polymer deposition occurs on the surfaces facing the plasma.
The above polymer deposition chemistry is very sensitive to the wafer temperature, such as deposition rate increase with a decrease of the wafer temperature. Here the surface can be any material such as wafer or other surfaces facing the plasma. This means, if the surface temperature is higher, most of the polymer deposition radicals that bombard on the surface are reflected back to the plasma. This causes an increase of polymer depositing radicals in the plasma at the vicinity of heated surfaces. Conversely, at the vicinity of cold surfaces, the concentration of polymer depositing radicals is lower. The concentration of polymer depositing radicals in the plasma greatly affects the etching rate and etching profile on the wafer surface. Therefore, over the entire wafer surface it is essential to have a constant polymer depositing radical concentration.
The temperature of the electrode 101 shown in FIG. 6 is controlled by flowing a liquid through the canals 107. Therefore, wafer temperature is controlled throughout the etching process. However, the temperature of the outer-ring 103 gradually increases as it is exposed to the plasma, because the outer-ring 103 is simply placed on the insulating material 104 and it is a replacement part. This causes a bigger difference of temperatures between the outer-ring 103 and the wafer. As a result, the gas chemistries over the outer-ring 103 and the wafer become different. The gas chemistry over the outer-ring greatly affects the process chemistry on the outermost region of the wafer. Therefore, the process chemistry at the central region and at the outer region of the wafer becomes different and hence cannot be used in device fabrication, as there is no uniform process over the wafer surface.
FIG. 7 shows another conventional wafer stage used in dielectric etching as the second example. In the structure shown in FIG. 7, components substantially identical to the components shown in FIG. 6 are respectively designated by the same reference numerals. In the second example shown in FIG. 7, the electrode 101 and modification of the thin dielectric plate 102 are expanded more than the diameter of the wafer. When the rf power is applied to the electrode 101, both the wafer and the outer-ring 103 get electrostatically clamped on the dielectric plate 102. This increases the thermal conductance between the outer-ring 103 and the electrode 101. Therefore, the outer-ring 103 also gets the same temperature as that of the wafer. This eliminates the generation of different gas chemistries on the wafer and the outer-ring 103.
However, there is a problem in this structure too. This problem is explained with reference to FIG. 8 showing an enlarged view of a part of the outer-ring 103 and the dielectric plate 102. As mentioned before, during the etching process, the polymer is deposited on the surfaces that face the plasma. With an increase of etching time, the polymer 111 is deposited within the small cavity 112 between the outer-ring 103 and the dielectric plate 102. When the wafers are running, the outer-ring 103 gets clamped and de-clamped repeatedly with the change of each wafer. Continuous clamping and de-clamping causes minute movements of the outer-ring 103. This generates small polymer particles and a few of these particles may go between the outer-ring 103 and the dielectric plate 102. When the polymer particles lie between the outer-ring 103 and the dielectric plate 102, electrostatic clamping does not work. In this case the temperature of the outer-ring rises. This results in different gas chemistries over the outer-ring 103 and the wafer due to the reasons mentioned before.
Accordingly, even electrostatic clamping of the outer-ring 103 is not a promising technique to control the outer-ring temperature. Further, even though the problems in controlling the outer-ring temperature is explained with reference to a dielectric etching system, the same problem can be seen in numerous other plasma processing systems.
Three patent documents, that is JP-A-7-86382, JP-A-6-61336 and JP-A-5-291194 disclose wafer or substrate holding stages similar to the above-mentioned conventional structures as to the wafer stage. Further, as a related art, JP-A-9-134892 discloses the mechanism for fixing a wafer on a table using a magnet. The magnet is used for fixing a ring member disposed around the wafer at lower side. The above fixing mechanism is built in a dicing machine that is considerably different from the plasma-assisted wafer processing system.
The subject of the present invention is to solve the above problems and to surely fix the outer-ring to the electrode of the wafer stage by using the magnet force and to improve the thermal conductance between the outer-ring and the electrode. Thereby the temperature of the outer-ring is controlled to be a desired temperature.